Six-transistor thyristor SRAM circuits and methods of operation
US9496020B2 · kind B2 · utility
10Cited by
9References
18Claims
0Family size
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Key dates
| Filing date | Jun 15, 2015 |
| Grant date | Nov 15, 2016 |
| Priority date | — |
| Expiry date | Jun 15, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/673
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory cell based upon cross-coupled thyristors for an SRAM integrated circuit can be implemented in different combinations of MOS and bipolar select transistors with the thyristors in a semiconductor substrate with shallow trench isolation. Standard CMOS process technology can be used to manufacture the SRAM cells.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.