Method of forming split-gate memory cell array along with low and high voltage logic devices

US9496369B2 · kind B2 · utility

Assignee

• Silicon Storage Technology, Inc. · US

Inventors

• Man-Tang Wu · Hengshan, TW
• Jeng-Wei Yang · Zhubei City, TW
• Chien-Sheng Su · Saratoga, US
• Chun-Ming Chen · Boise, US
• Nhan Do · Saratoga, US

Key dates

• Filing date: Jan 20, 2016
• Grant date: Nov 15, 2016
• Expiry date: Jan 20, 2036

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D64/035

Abstract

A method of forming a memory device on a substrate having memory, LV and HV areas, including forming pairs of spaced apart memory stacks in the memory area, forming a first conductive layer over and insulated from the substrate, forming a first insulation layer on the first conductive layer and removing it from the memory and HV areas, performing a conductive material deposition to thicken the first conductive layer in the memory and HV areas, and to form a second conductive layer on the first insulation layer in the LV area, performing an etch to thin the first conductive layer in the memory and HV areas and to remove the second conductive layer in the LV area, removing the first insulation layer from the LV area, and patterning the first conductive layer to form blocks of the first conductive layer in the memory, LV and HV areas.