Translation lookaside buffer management
US9501425B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 14, 2014 |
| Grant date | Nov 22, 2016 |
| Priority date | — |
| Expiry date | Jan 23, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/683
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Each of multiple translation lookaside buffers (TLBs) is associated with a corresponding processing element. A first TLB invalidation (TLBI) instruction is issued at a first processing element, and sent to a second processing element. An element-specific synchronization instruction is issued at the first processing element. A synchronization command is broadcast, and received at the second processing element. The element-specific synchronization instruction prevents issuance of additional TLBI instructions at the first processing element until an acknowledgement in response to the synchronization command is received at the first processing element. After completion of any TLBI instructions issued at the second processing element before the synchronization command was received, the acknowledgement is sent from the second processing element to the first processing element, indicating that any TLBI instructions issued at the second processing element before the synchronization command was received at the second processing element are complete.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.