Methods for forming interconnection structures in an integrated cluster system for semicondcutor applications
US9508561B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 13, 2014 |
| Grant date | Nov 29, 2016 |
| Priority date | — |
| Expiry date | Aug 29, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76885
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Embodiments of the present invention provide methods for forming an interconnection structure in semiconductor devices without breaking vacuum with minimum oxidation/atmosphere exposure. In one embodiment, a method for forming an interconnection structure for semiconductor devices includes supplying a barrier layer etching gas mixture into a first processing chamber having a substrate disposed therein to etch portions of a barrier layer exposed by a patterned metal layer until the underlying substrate is exposed, the first processing chamber disposed in a processing system, and forming a liner layer on the substrate covering the etched barrier layer in a second processing chamber disposed in the processing system.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.