Methods of forming punch through stop regions on FinFET devices on CMOS-based IC products using doped spacers
US9508604B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 29, 2016 |
| Grant date | Nov 29, 2016 |
| Priority date | — |
| Expiry date | Apr 29, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/853
Abstract
One illustrative method disclosed herein includes, among other things, forming a first plurality of fins for a type 1 device and a second plurality of fins for a type 2 device, forming a first counter-doped sidewall spacer structure adjacent the first fins, forming a second counter-doped sidewall spacer structure adjacent the second fins and a counter-doped material structure in a space between the first fins, forming a recessed layer of flowable oxide on the devices such that portions of the first and second counter-doped sidewall spacers are exposed above the flowable oxide layer, and performing a common etching process operation to remove at least a portion of the exposed portions of the first and second counter-doped sidewall spacer structures.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.