Nanosheet MOSFET with full-height air-gap spacer
US9508829B1 · kind B1 · utility
18Cited by
0References
14Claims
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Assignee
Inventors
Key dates
| Filing date | May 4, 2016 |
| Grant date | Nov 29, 2016 |
| Priority date | — |
| Expiry date | May 4, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/121
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor device includes a gate positioned on a substrate; a nanosheet that extends through the gate, protrudes from a sidewall of the gate, and forms a recess between the substrate and the nanosheet; a dielectric spacer disposed in the recess; a source/drain contact positioned on a source/drain disposed on the substrate adjacent to the gate; an air gap spacer positioned along the sidewall of the gate and in contact with a dielectric material disposed on the nanosheet, the air gap spacer being in contact with the source/drain contact; and an interlayer dielectric (ILD) disposed on the air gap spacer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.