Multi-clock generation through phase locked loop (PLL) reference
US9514831B2 · kind B2 · utility
1Cited by
15References
18Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jan 14, 2015 |
| Grant date | Dec 6, 2016 |
| Priority date | — |
| Expiry date | Jan 14, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/0891
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A circuit for providing a plurality of clock signals of differing frequencies includes: a phase locked loop section including a first voltage controller oscillator, connected to receive a reference clock value and generate therefrom a first voltage level, wherein the first voltage controller oscillator receives the first voltage level and generates therefrom a first clock signal; and one or more second voltage controller oscillators, each connected to receive the first voltage level, a corresponding trim value and a corresponding control voltage and derive therefrom a corresponding second clock signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.