Patent · US Active

Method of forming a gate mask for fabricating a structure of gate lines

US9514942B1 · kind B1 · utility

4Cited by
7References
20Claims
0Family size

Assignee

Inventors

Key dates

Filing dateMar 3, 2016
Grant dateDec 6, 2016
Priority date
Expiry dateMar 3, 2036

Classification

  • Technology area (CPC H)Electricity
  • CPC primaryH10D84/0135
  • WIPO fieldSemiconductors
  • WIPO sectorElectrical engineering

Abstract

A method of forming a gate structure over a hybrid substrate structure with topography having a bulk region and an SOI region is disclosed including forming a gate material layer above the SOI and bulk regions, forming a mask layer above the gate material layer, forming a first planarization layer above the mask layer, forming a first gate structure masking pattern above the first planarization layer, patterning the first planarization layer in alignment with the first gate structure masking pattern, and patterning the mask layer in accordance with the patterned first planarization layer, resulting in a gate mask disposed above the gate material layer.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.