Magnetic random access memory (MRAM) and method of operation
US9520173B1 · kind B1 · utility
15Cited by
6References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Feb 29, 2016 |
| Grant date | Dec 13, 2016 |
| Priority date | — |
| Expiry date | Feb 29, 2036 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2213/79
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory device includes a first memory cell having a first transistor, a second transistor, and a resistive storage element. During a read operation, sense current is conducted through the second transistor and the first transistor is used to sense feedback voltage at a first terminal of the resistive storage element. During a write operation, current is conducted through the first and second transistors.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.