Method for creating self-aligned SDB for minimum gate-junction pitch and epitaxy formation in a fin-type IC device
US9524911B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 18, 2015 |
| Grant date | Dec 20, 2016 |
| Priority date | — |
| Expiry date | Sep 18, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/834
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Methods for creating self-aligned FINFET SDBs for minimum gate junction pitch and epitaxy formation. Embodiments include forming separated openings in a hard mask on upper surfaces of Si fins; forming cavities in the fins, each of the cavities having a concave shape and a width extending under the hard mask on each side of the cavity; forming trenches in the fins, the trenches having an upper width substantially equal to a width of the openings and less than the width of a cavity; removing the hard mask; filling the trenches and the cavities with oxide, forming STI regions; forming an oxide mask layer on the upper surfaces of the fins and the STI regions; removing upper portions of the oxide in sections between the STI regions; and removing remaining portions of the oxide mask revealing the fins and upper surfaces of the STI regions.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.