Patent · US Active

Filling cavities in an integrated circuit and resulting devices

US9524935B2 · kind B2 · utility

6Cited by
5References
13Claims
0Family size

Assignee

Inventors

Key dates

Filing dateMay 13, 2015
Grant dateDec 20, 2016
Priority date—
Expiry dateMay 13, 2035

Classification

  • Technology area (CPC H)Electricity
  • CPC primaryH01L23/53295
  • WIPO fieldSemiconductors
  • WIPO sectorElectrical engineering

Abstract

A methodology enabling filling of high aspect ratio cavities, with no voids or gaps, in an IC device and the resulting device are disclosed. Embodiments include providing active area and/or gate contacts in a first ILD; forming selective protective caps on upper surfaces of the contacts; forming a second ILD on upper surfaces of the protective caps and on an upper surface of the first ILD; forming a hard-mask stack on the second ILD; forming, in the second ILD and hard-mask stack, cavities exposing one or more protective caps; removing selective layers in the stack to decrease depths of the cavities; and filling the cavities with a metal layer, wherein the metal layer in one or more cavities connects to an upper surface of the one or more exposed protective caps.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.