Three-dimensional memory devices having a single layer channel and methods of making thereof

US9530785B1 · kind B1 · utility

Assignee

• Sandisk Technologies, Inc. · US

Inventors

• Sateesh Koka · Milpitas, US
• Zhenyu Lu · Hubei, CN
• Wei Zhao · Milpitas, US
• Ching-Huang Lu · Taoyuan, TW
• Henry Chien · San Jose, US
• Yingda Dong · San Jose, US
• Raghuveer S. Makala · Campbell, US
• Somesh Peri · San Jose, US
• Rahul Sharangpani · Fremont, US
• George Matamis · Danville, US
• Yuichi Ikezono · Yokkaichi, JP
• Hiroyuki Ogawa · Nagoya, JP

Key dates

• Filing date: Jul 21, 2015
• Grant date: Dec 27, 2016
• Expiry date: Jul 21, 2035

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D88/00

Abstract

A memory stack structure for a three-dimensional device includes an alternating stack of insulator layers and spacer material layers. A memory opening is formed through the alternating stack. A memory material layer, a tunneling dielectric layer, and a silicon oxide liner are formed in the memory opening. A sacrificial liner is subsequently formed over the tunneling dielectric layer. The layer stack is anisotropically etched to physically expose a semiconductor surface of the substrate underneath the memory opening. The sacrificial liner may be removed prior to, or after, the anisotropic etch. The silicon oxide liner is removed after the anisotropic etch. A semiconductor channel layer can be deposited directly on the tunneling dielectric layer as a single material layer without any interface therein.