Hybrid exposure for semiconductor devices

US9543224B1 · kind B1 · utility

Assignee

• Intel IP Corporation · US

Inventors

• Thorsten Meyer · Regensburg, DE
• Gerald Ofner · Regensburg, DE
• Robert L. Sankman · Phoenix, US

Key dates

• Filing date: Dec 9, 2015
• Grant date: Jan 10, 2017
• Expiry date: Dec 9, 2035

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L2924/18162
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

Semiconductor packages and methods, systems, and apparatuses of forming such packages are described. A method of forming a semiconductor package may include encapsulating a semiconductor die with a molding compound, applying a seed layer on the die and the molding compound, applying a resist layer on the seed layer, exposing a first portion of the resist layer, and exposing a second portion of the resist layer. The first portion can include a first area of the resist layer to be used for forming a redistribution layer (RDL) without including a second area of the resist layer to be used for forming an electrical communications pathway between at least one of the contact pads and the RDL. The second portion can include the second area of the resist layer that includes the electrical communications pathway.