Patent · US Active

Memory device with timing overlap mode and precharge timing circuit

US9552849B2 · kind B2 · utility

2Cited by

5References

20Claims

0Family size

Assignee

Everspin Technologies, Inc. · US

Inventors

Thomas Andre · Austin, US
Syed M. Alam · Austin, US
Halbert S. Lin · Austin, US

Key dates

Filing date	Dec 18, 2015
Grant date	Jan 24, 2017
Priority date	—
Expiry date	Dec 18, 2035

Classification

Technology area (CPC G)Physics
CPC primaryG11C11/4076
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

In some examples, a memory device is configured to receive a precharge command and an activate command. The memory device performs a first series of events related to the precharge command in response to receiving the precharge command and a second series of events related to the activate command in response to receiving the activate command. The memory device delays the start of the second series of events until the first series of events completes.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.