Trench vertical NAND and method of making thereof
US9552991B2 · kind B2 · utility
2Cited by
21References
7Claims
0Family size
Assignee
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Key dates
| Filing date | Apr 30, 2014 |
| Grant date | Jan 24, 2017 |
| Priority date | — |
| Expiry date | Jan 30, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/037
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of making a monolithic three dimensional NAND string includes providing a stack of alternating first material layers and second material layers different from the first material layer over a substrate, etching the stack to form at least one trench in the stack, forming a blocking dielectric over a side wall of the at least one trench, forming a charge storage layer over the blocking dielectric in the at least one trench, forming a tunnel dielectric over the charge storage layer in the at least one trench and forming a semiconductor channel over the tunnel dielectric in the at least one trench.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.