Airgap protection layer for via alignment
US9553019B1 · kind B1 · utility
15Cited by
12References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Apr 15, 2016 |
| Grant date | Jan 24, 2017 |
| Priority date | — |
| Expiry date | Apr 15, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L23/53295
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for via alignment includes forming first airgaps between interconnect structures and depositing a pinch off layer to close off openings to the first airgaps. A protection layer is formed in divots in the pinch off layer. The protection layer and the pinch off layer are planarized to form a surface where the protection layer remains in the divots. An interlevel dielectric layer (ILD) is deposited on the surface. The ILD and the pinch off layer are etched using the protection layer as an etch stop to align a via and expose the interconnect structure through the via.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.