Method and structure for multi-core chip product test and selective voltage binning disposition
US9557378B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 20, 2012 |
| Grant date | Jan 31, 2017 |
| Priority date | — |
| Expiry date | Aug 8, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F1/32
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
Operating speeds of integrated circuit devices are tested to establish maximum and minimum frequency at maximum and minimum voltage. The devices are sorted into relatively-slow and relatively-fast devices to classify the devices into different voltage bins. A bin-specific voltage limit is established for each of the voltage bins needed for core performance at system use conditions. The bin-specific voltage limit is compared to core minimum chip-level functionality voltage at system maximum and minimum frequency specifications. The method correlates system design evaluation of design maximum and minimum frequency at design maximum and minimum voltage conditions with evaluation of tested maximum and minimum frequency at tested maximum and minimum voltage conditions. A chip-specific functionality voltage limit is established for the device. Initial system voltage for all devices from a voltage bin is set at a greater of the bin-specific voltage limit and the chip-specific functionality voltage limit consistent with the evaluation conditions.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.