Instruction and logic for a cache prefetcher and dataless fill buffer

US9558127B2 · kind B2 · utility

Assignee

• Intel Corporation · US

Inventors

• Stanislav Shwartsman · Haifa, IL
• Robert S. Chappell · Portland, US
• Ronak Singhal · Portland, US
• Ryan Carlson · Hillsboro, US
• Raanan Sade · Migdal HaEmek, IL
• Omar M. Shaikh · Portland, US
• Liron Zur · Haifa, IL
• Yiftach Gilad · Givat Ada, IL

Key dates

• Filing date: Sep 9, 2014
• Grant date: Jan 31, 2017
• Expiry date: Apr 18, 2035

Classification

• Technology area (CPC G): Physics
• CPC primary: G06F2212/602
• WIPO field: Computer technology
• WIPO sector: Electrical engineering

Abstract

A processor includes a cache hierarchy and an execution unit. The cache hierarchy includes a lower level cache and a higher level cache. The execution unit includes logic to issue a memory operation to access the cache hierarchy. The lower level cache includes logic to determine that a requested cache line of the memory operation is unavailable in the lower level cache, determine that a line fill buffer of the lower level cache is full, and initiate prefetching of the requested cache line from the higher level cache based upon the determination that the line fill buffer of the lower level cache is full. The line fill buffer is to forward miss requests to the higher level cache.