Six-transistor SRAM semiconductor structures and methods of fabrication
US9564198B2 · kind B2 · utility
9Cited by
32References
13Claims
0Family size
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Key dates
| Filing date | Jun 15, 2015 |
| Grant date | Feb 7, 2017 |
| Priority date | — |
| Expiry date | Jun 15, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/131
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A two-transistor memory cell based upon a thyristor for an SRAM integrated circuit is described together with a process for fabricating it. The memory cell can be implemented in different combinations of MOS and bipolar select transistors, or without select transistors, with thyristors in a semiconductor substrate with shallow trench isolation. Standard CMOS process technology can be used to manufacture the SRAM.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.