Smart verify for programming non-volatile memory
US9564226B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 30, 2015 |
| Grant date | Feb 7, 2017 |
| Priority date | — |
| Expiry date | Oct 30, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/3459
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Techniques are provided for reducing current consumption while programming non-volatile storage. A smart verify is performed using a subset of memory cells. By applying the smart verify to just a subset of the memory cells current is saved. The smart verify may be used to characterize programming speed. Results of the smart verify may be used to determine a magnitude of a dummy program pulse to be applied later in the programming process. The dummy program pulse is not followed by a program verify, which reduces current. If the dummy program pulse pushes threshold voltages high enough, then those memory cells will not conduct a current when verifying later in programming. Thus, current is saved during the program verify. Also, bit lines of memory cells that received the dummy pulses do not need to be pre-charged prior to a program pulse, which can save more current.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.