Method of forming magnetic tunneling junctions
US9564582B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 7, 2014 |
| Grant date | Feb 7, 2017 |
| Priority date | — |
| Expiry date | Apr 11, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B61/00
Abstract
A method for fabricating an MRAM bit that includes depositing a spacer layer that protects the tunneling barrier layer during processing is disclosed. The deposited spacer layer prevents byproducts formed in later processing from redepositing on the tunneling barrier layer. Such redeposition may lead to product failure and decreased manufacturing yield. The method further includes non-corrosive processing conditions that prevent damage to the layers of MRAM bits. The non-corrosive processing conditions may include etching without using a halogen-based plasma. Embodiments disclosed herein use an etch-deposition-etch sequence that simplifies processing.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.