Scan wrapper circuit for integrated circuit
US9568551B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 16, 2015 |
| Grant date | Feb 14, 2017 |
| Priority date | — |
| Expiry date | Sep 16, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/318572
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
An integrated circuit (IC), operable in internal and external testing modes (INTEST and EXTEST), includes first and second partitions and a functional path therebetween. The first partition includes a first scan chain, a first multiplexer, and a first flip-flop. The second partition includes a second flip-flop and a second scan chain. The first scan chain generates an EXTEST vector initialization signal, based on an EXTEST scan input signal. The first multiplexer receives an INTEST vector initialization signal and the EXTEST vector initialization signal, and generates a scan input signal. The first flip-flop generates a first output signal based on the scan input signal. The functional path provides a second output signal based on the first output signal. The second flip-flop generates a third output signal based on the second output signal. The second scan chain receives the third output signal and generates a test output signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.