Methods of forming transistor structures including forming channel material after formation processes to prevent damage to the channel material
US9570588B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 14, 2015 |
| Grant date | Feb 14, 2017 |
| Priority date | — |
| Expiry date | Oct 14, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/6218
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Methods for fabricating transistor structures are provided, the methods including: forming a fin structure with an upper fin portion and a lower fin portion, the upper fin portion including a sacrificial material; forming a gate structure over the fin; selectively removing the upper fin portion to form a tunnel between the gate structure and lower fin portion; and providing a channel material in the tunnel to define the channel region of the gate structure. The sacrificial material may be a material that can be selectively etched without etching the material of the lower fin portion. The channel material may further be provided to form source and drain regions of the transistor structure, which may result in a junctionless FinFET structure.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.