Resistive random access memory
US9570681B2 · kind B2 · utility
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6References
14Claims
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Key dates
| Filing date | Sep 19, 2014 |
| Grant date | Feb 14, 2017 |
| Priority date | — |
| Expiry date | Jan 29, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A resistive random access memory may include a memory array and a periphery around the memory array. Decoders in the periphery may be coupled to address lines in the array by forming a metallization in the periphery and the array at the same time using the same metal deposition. The metallization may form row lines in the array.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.