Low forming voltage non-volatile storage device
US9576660B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 14, 2016 |
| Grant date | Feb 21, 2017 |
| Priority date | — |
| Expiry date | Jan 14, 2036 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2213/77
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A three-dimensional array of memory elements that reversibly change a level of electrical conductance in response to a voltage difference being applied across them. The memory elements can be set to a low resistance state and reset to a high resistance state during standard operation by biasing appropriate voltages on the word lines and bit lines. Prior to standard operation, the memory elements undergo a forming operation, during which current through the bit lines is limited. A forming voltage is applied to the memory elements during forming with a polarity such that a higher voltage is applied to anodes and a lower voltage to cathodes.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.