Semiconductor device and method comprising redistribution layers
US9576919B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 2, 2015 |
| Grant date | Feb 21, 2017 |
| Priority date | — |
| Expiry date | Nov 2, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/3511
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of making a semiconductor package can include forming a plurality of redistribution layer (RDL) traces disposed over active surfaces of a plurality of semiconductor die and electrically connected to contact pads on the plurality of semiconductor die. The method can include disposing an encapsulant material over the active surfaces, contacting at least four side surfaces of each of the plurality of semiconductor die, and disposed over the plurality of RDL traces. The method can also include forming a via through the encapsulant material to expose at least one of the plurality of RDL traces, forming an electrical interconnect disposed within the via and coupled to the at least one RDL trace, and singulating the plurality of semiconductor packages through the encapsulant material to leave an offset of 30-140 μm of the encapsulant material disposed around a periphery of each of the plurality of semiconductor die.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.