Methods, apparatus and system for voltage ramp testing
US9599656B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Nov 25, 2014 |
| Grant date | Mar 21, 2017 |
| Priority date | — |
| Expiry date | Oct 14, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/2879
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
At least one method and system disclosed herein involves testing of integrated circuits. A device having at least one transistor and at least one dielectric layer is provided. A first voltage is provided during a first time period for performing a stress test upon the device. A second voltage is provided during a second time period for discharging at least a portion of the charge built-up as a result of the first voltage. The second voltage is of an opposite polarity of the first voltage. A sense function is provided during a third time period for determining a result of the stress test. Data relating to a breakdown of the dielectric layer based upon the result of the stress test is acquired, stored and/or transmitted.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.