Alternating space decomposition in circuit structure fabrication
US9606432B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 5, 2014 |
| Grant date | Mar 28, 2017 |
| Priority date | — |
| Expiry date | Nov 5, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG03F7/203
- WIPO fieldOptics
- WIPO sectorInstruments
Abstract
Fabrication of a circuit structure is facilitated, in which a first exposure of a multi-layer structure is performed using a first mask, which defines positioning of at least one edge of an element to be formed above a substrate of the multi-layer structure. A second exposure of the multi-layer structure is performed using a second mask, which defines positioning of at least one other edge of the element. At least some material of the multi-layer structure is removed using, at least in part, the defined positioning of the at least one edge and the at least one other edges of the element, to form the element above the substrate. In some examples, multiple elements are formed, the multiple elements being hardmask elements to facilitate an etch process to etch a substrate material.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.