Semiconductor devices with back surface isolation
US9607876B2 · kind B2 · utility
8Cited by
8References
31Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 14, 2011 |
| Grant date | Mar 28, 2017 |
| Priority date | — |
| Expiry date | Dec 14, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/475
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Circuits, structures and techniques for independently connecting a surrounding material in a part of a semiconductor device to a contact of its respective device. To achieve this, a combination of one or more conductive wells that are electrically isolated in at least one bias polarity are provided.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.