Implementing stress in a bipolar junction transistor
US9608096B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 2, 2015 |
| Grant date | Mar 28, 2017 |
| Priority date | — |
| Expiry date | Oct 2, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/137
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Device structure and fabrication methods for a bipolar junction transistor. One or more trench isolation regions are formed in a substrate to define a device region having a first width. A protect layer is formed on a top surface of the one or more trench isolation regions and a top surface of the device region. An opening is formed in the protect layer. The opening is coincides with the top surface of the first device region and has a second width that is less than or equal to the first width of the first device region. A base layer is formed that has a first section on the device region inside the first opening and a second section on the protect layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.