Integrated circuit with selectable power-on reset mode
US9612653B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 3, 2015 |
| Grant date | Apr 4, 2017 |
| Priority date | — |
| Expiry date | Sep 8, 2035 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An integrated circuit (IC) and associated method support using a pre-use configuration for determining an initial/preferred operational mode for the IC from plural operational modes that may be entered following power-up cycles of the IC. The initial/preferred operational mode can be determined after the design phase of the IC so that, during IC operation, wasted power or delay are not incurred by first requiring that the IC power up in a default operational mode and subsequently run executive code to reprogram the IC to enter an operational mode that is preferred for the application for which the IC is being used by the IC integrator/user. The configurations determine clock frequencies and/or power levels for core processing and/or peripheral modules and allow the same IC design/die to be targeted to a spectrum of different power usage/performance applications by the integrator/user.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.