Encapsulated dies with enhanced thermal performance
US9613831B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 4, 2015 |
| Grant date | Apr 4, 2017 |
| Priority date | — |
| Expiry date | Dec 4, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/15313
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The present disclosure relates to enhancing the thermal performance of encapsulated flip chip dies. According to an exemplary process, a plurality of flip chip dies are attached on a top surface of a carrier, and a first mold compound is applied over the top surface of the carrier to encapsulate the plurality of flip chip dies. The first mold compound is thinned down to expose a substrate of each flip chip die and the substrate of each flip chip die is then substantially etched away to provide an etched flip chip die that has an exposed surface at the bottom of a cavity. Next, a second mold compound with high thermal conductivity is applied to substantially fill each cavity and the top surface of the second mold compound is planarized. Finally, the encapsulated etched flip chip dies can be marked, singulated, and tested as a module.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.