Junction butting structure using nonuniform trench shape
US9627480B2 · kind B2 · utility
6Cited by
25References
11Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 26, 2014 |
| Grant date | Apr 18, 2017 |
| Priority date | — |
| Expiry date | Feb 3, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D86/201
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The present invention relates generally to semiconductor devices and more particularly, to a structure and method of forming a partially depleted semiconductor-on-insulator (SOI) junction isolation structure using a nonuniform trench shape formed by reactive ion etching (RIE) and crystallographic wet etching. The nonuniform trench shape may reduce back channel leakage by providing an effective channel directly below a gate stack having a width that is less than a width of an effective back channel directly above the isolation layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.