Error handling in transactional buffered memory
US9632862B2 · kind B2 · utility
1Cited by
7References
18Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 20, 2014 |
| Grant date | Apr 25, 2017 |
| Priority date | — |
| Expiry date | Mar 20, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L2001/0097
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
Data is sent from a memory buffer device to a host device over a link. An error in the data is determined. A read response cancellation signal is sent to the host device to indicate the error to the host device, where the read response cancellation signal is to be sent subsequent to the data being sent from the memory buffer device to the host device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.