System and method to inhibit erasing of portion of sector of split gate flash memory cells
US9633735B2 · kind B2 · utility
1Cited by
4References
2Claims
0Family size
Assignee
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Key dates
| Filing date | Sep 15, 2014 |
| Grant date | Apr 25, 2017 |
| Priority date | — |
| Expiry date | Sep 15, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/028
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system and method to inhibit the erasing of a portion of a sector of split gate flash memory cells while allowing the remainder of the sector to be erased is disclosed. The inhibiting is controlled by control logic that applies one or more bias voltages to the portion of the sector whose erasure is to be inhibited.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.