Cu/barrier interface enhancement
US9633861B2 · kind B2 · utility
2Cited by
0References
8Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Feb 13, 2014 |
| Grant date | Apr 25, 2017 |
| Priority date | — |
| Expiry date | Dec 23, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76834
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Embodiments of the present invention provide processes to selectively form a metal layer on a conductive surface, followed by flowing a silicon based compound over the metal layer to form a metal silicide layer. In one embodiment, a substrate having a conductive surface and a dielectric surface is provided. A metal layer is then deposited on the conductive surface. A metal silicide layer is formed as a result of flowing a silicon based compound over the metal layer. A dielectric is formed over the metal silicide layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.