Plug via formation with grid features in the passivation layer
US9633962B2 · kind B2 · utility
0Cited by
19References
17Claims
0Family size
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Key dates
| Filing date | Oct 8, 2013 |
| Grant date | Apr 25, 2017 |
| Priority date | — |
| Expiry date | Dec 17, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/14
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Solder bump connections and methods for fabricating solder bump connections. A passivation layer is formed on a dielectric layer. Via openings extend through the passivation layer from a top surface of the passivation layer to a metal line in the passivation layer. A conductive layer is formed on the top surface of the passivation layer and within each via opening. When the passivation layer and the conductive layer are planarized, a plug is formed that includes sections in the via openings. Each section is coupled with the metal line.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.