Trench confined epitaxially grown device layer(s)

US9634007B2 · kind B2 · utility

Assignee

• Intel Corporation · US

Inventors

• Ravi Pillarisetty · Portland, US
• Seung Hoon Sung · Beaverton, US
• Niti Goel · Portland, US
• Jack T. Kavalieros · Portland, US
• Sansaptak Dasgupta · Hillsboro, US
• Van H. Le · Portland, US
• Willy Rachmady · Beaverton, US
• Marko Radosavljevic · Portland, US
• Gilbert Dewey · Beaverton, US
• Han Wui Then · Portland, US
• Niloy Mukherjee · Beaverton, US
• Matthew V. Metz · Portland, US
• Robert S. Chau · Beaverton, US

Key dates

• Filing date: Jun 11, 2014
• Grant date: Apr 25, 2017
• Expiry date: Jun 11, 2034

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D84/038
• WIPO field: Micro-structural and nano-technology
• WIPO sector: Chemistry

Abstract

Trench-confined selective epitaxial growth process in which epitaxial growth of a semiconductor device layer proceeds within the confines of a trench. In embodiments, a trench is fabricated to include a pristine, planar semiconductor seeding surface disposed at the bottom of the trench. Semiconductor regions around the seeding surface may be recessed relative to the seeding surface with Isolation dielectric disposed there on to surround the semiconductor seeding layer and form the trench. In embodiments to form the trench, a sacrificial hardmask fin may be covered in dielectric which is then planarized to expose the hardmask fin, which is then removed to expose the seeding surface. A semiconductor device layer is formed from the seeding surface through selective heteroepitaxy. In embodiments, non-planar devices are formed from the semiconductor device layer by recessing a top surface of the isolation dielectric. In embodiments, non-planar devices CMOS devices having high carrier mobility may be made from the semiconductor device layer.