CMOS in situ doped flow with independently tunable spacer thickness
US9634103B2 · kind B2 · utility
4Cited by
1References
13Claims
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Key dates
| Filing date | Apr 3, 2013 |
| Grant date | Apr 25, 2017 |
| Priority date | — |
| Expiry date | Apr 3, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/038
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for manufacturing a microelectronic device with transistors of different types having raised source and drain regions and different overlap regions.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.