Wire bond free wafer level LED
US9634191B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 14, 2007 |
| Grant date | Apr 25, 2017 |
| Priority date | — |
| Expiry date | Nov 14, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10H20/8506
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A wire-bond free semiconductor device with two electrodes both of which are accessible from the bottom side of the device. The device is fabricated with two electrodes that are electrically connected to the oppositely doped epitaxial layers, each of these electrodes having leads with bottom-side access points. This structure allows the device to be biased with an external voltage/current source, obviating the need for wire-bonds or other such connection mechanisms that must be formed at the packaging level. Thus, features that are traditionally added to the device at the packaging level (e.g., phosphor layers or encapsulants) may be included in the wafer level fabrication process. Additionally, the bottom-side electrodes are thick enough to provide primary structural support to the device, eliminating the need to leave the growth substrate as part of the finished device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.