Compact model for device/circuit/chip leakage current (IDDQ) calculation including process induced uplift factors
US9639652B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 6, 2014 |
| Grant date | May 2, 2017 |
| Priority date | — |
| Expiry date | Oct 29, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/3008
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system, method and computer program product for implementing a quiescent current leakage specific model into semiconductor device design and circuit design flows. The leakage model covers all device geometries with wide temperature and voltage ranges and, without the need for stacking factor calculations nor spread sheet based IDDQ calculations. The leakage model for IDDQ calculation incorporates further parasitic and proximity effects. The leakage model implements leakage calculations at different levels of testing, e.g., from a single device to a full chip design, and are integrated within one single model. The leakage model implements leakage calculations at different levels of testing with the leverage of a single switch setting. The implementation is via a hardware definition language code or object oriented code that can be compiled and operated using a netlist of interest, e.g., for conducting a performance analysis.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.