Method of forming a semiconductor structure including silicided and non-silicided circuit elements

US9646838B2 · kind B2 · utility

Assignee

• GlobalFoundries Inc. · KY

Inventors

• Dominic Thurmer · Dresden, DE
• Sven Metzger · Dresden, DE
• Joachim Patzer · Rohrbach, DE
• Markus Lenski · Dresden, DE

Key dates

• Filing date: Jun 2, 2014
• Grant date: May 9, 2017
• Expiry date: Apr 29, 2035

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D30/792
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

A method includes providing a semiconductor structure including at least one first circuit element including a first semiconductor material and at least one second circuit element including a second semiconductor material. A dielectric layer having an intrinsic stress is formed that includes a first portion over the at least one first circuit element and a second portion over the at least one second circuit element. A first annealing process is performed, wherein an intrinsic stress is created at least in the first semiconductor material by stress memorization, and thereafter the first portion of the dielectric layer is removed. A layer of a metal is formed, and a second annealing process is performed, wherein the metal and the first semiconductor material react chemically to form a silicide. The second portion of the dielectric layer substantially prevents a chemical reaction between the second semiconductor material and the metal.