Methods of forming buried vertical capacitors and structures formed thereby
US9646972B2 · kind B2 · utility
1Cited by
18References
22Claims
0Family size
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Key dates
| Filing date | Sep 25, 2013 |
| Grant date | May 9, 2017 |
| Priority date | — |
| Expiry date | Sep 25, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B12/038
Abstract
Methods of forming passive elements under a device layer are described. Those methods and structures may include forming at least one passive structure, such as a capacitor and a resistor structure, in a substrate, wherein the passive structures are vertically disposed within the substrate. An insulator layer is formed on a top surface of the passive structure, a device layer is formed on the insulator layer, and a contact is formed to couple a device disposed in the device layer to the at least one passive structure.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.