Fully associative cache memory budgeted by memory access type
US9652400B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 14, 2014 |
| Grant date | May 16, 2017 |
| Priority date | — |
| Expiry date | Dec 14, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/604
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A fully associative cache memory, comprising: an array of storage elements; an allocation unit that allocates the storage elements in response to memory accesses that miss in the cache memory. Each memory access has an associated memory access type (MAT) of a plurality of predetermined MATs. Each valid storage element of the array has an associated MAT. For each MAT, the allocation unit maintains: a counter that counts of a number of valid storage elements associated with the MAT; and a corresponding threshold. The allocation unit allocates into any of the storage elements in response to a memory access that misses in the cache, unless the counter of the MAT of the memory access has reached the corresponding threshold, in which case the allocation unit replaces one of the valid storage elements associated with the MAT of the memory access.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.