Methods for etching a hardmask layer for an interconnection structure for semiconductor applications
US9653320B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 24, 2014 |
| Grant date | May 16, 2017 |
| Priority date | — |
| Expiry date | Oct 29, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Embodiments of the present disclosure provide methods for patterning a hardmask layer disposed on a metal layer, such as a copper layer, to form an interconnection structure in semiconductor devices. In one embodiment, a method of patterning a hardmask layer on a metal layer disposed on a substrate includes supplying a first etching gas mixture comprising a carbon-fluorine containing gas and a chlorine containing gas into a processing chamber to etch a portion of a hardmask layer disposed on a metal layer formed on a substrate, supplying a second etching gas mixture comprising a hydrocarbon gas into the processing chamber to clean the substrate, and supplying a third etching gas mixture comprising a carbon-fluorine containing gas to remove a remaining portion of the hardmask layer until a surface of the metal layer is exposed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.