Integrated etch stop for capped gate and method for manufacturing the same
US9653547B1 · kind B1 · utility
15Cited by
9References
17Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 17, 2016 |
| Grant date | May 16, 2017 |
| Priority date | — |
| Expiry date | Mar 17, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D86/201
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor device includes a plurality of gate stacks spaced apart from each other on a substrate, an etch stop layer formed on an upper surface of each gate stack, a dielectric cap layer formed on each etch stop layer, a plurality of source/drain regions formed on the substrate between respective pairs of adjacent gate stacks, and a plurality of contacts respectively corresponding to each source/drain region, wherein the contacts are separated from the gate structures and contact their corresponding source/drain regions.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.