Method of manufacturing an insulated gate bipolar transistor with mesa sections between cell trench structures

US9653568B2 · kind B2 · utility

Assignee

• Infineon Technologies AG · DE

Inventors

• Johannes Georg Laven · Taufkirchen, DE
• Alexander Philippou · Munich, DE
• Hans-Joachim Schulze · Taufkirchen, DE
• Christian Jaeger · Munich, DE
• Roman Baburske · Otterfing, DE
• Antonio Vellei · Villach, AT

Key dates

• Filing date: Jun 9, 2015
• Grant date: May 16, 2017
• Expiry date: Jun 9, 2035

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D62/127
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

A method of manufacturing an insulated gate bipolar transistor includes providing trenches extending from a first surface to a layer section in a semiconductor portion, introducing impurities into mesa sections between the trenches, and forming, from the introduced impurities, second portions of doped regions separated from source regions by body regions. The source regions are electrically connected to an emitter electrode. The second portions have a second mean net impurity concentration exceeding at least ten times a first mean net impurity concentration in first portions of the doped layer. The first portions extend from the body regions to the layer section, respectively.