Techniques for filament localization, edge effect reduction, and forming/switching voltage reduction in RRAM devices

US9653680B2 · kind B2 · utility

Assignee

• Intel Corporation · US

Inventors

• Ravi Pillarisetty · Portland, US
• Prashant Majhi · San Jose, US
• Uday Shah · Portland, US
• Niloy Mukherjee · Beaverton, US
• Elijah V. Karpov · Portland, US
• Brian S. Doyle · Portland, US
• Robert S. Chau · Beaverton, US

Key dates

• Filing date: Jun 27, 2015
• Grant date: May 16, 2017
• Expiry date: Jun 27, 2035

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10N70/8833

Abstract

The present disclosure provides a system and method for forming a resistive random access memory (RRAM) device. A RRAM device consistent with the present disclosure includes a substrate and a first electrode disposed thereon. The RRAM device includes a second electrode disposed over the first electrode and a RRAM dielectric layer disposed between the first electrode and the second electrode. The RRAM dielectric layer has a recess at a top center portion at the interface between the second electrode and the RRAM dielectric layer.