Patent · US Active

Decimal and binary floating point rounding

US9658828B2 · kind B2 · utility

1Cited by

10References

12Claims

0Family size

Assignee

International Business Machines Corporation · US

Inventors

Steven R. Carlough · Poughkeepsie, US
Klaus M. Kroener · Ehningen, DE
Petra Leber · Ehningen, DE
Cedric Lichtenau · Stuttgart, DE
Silvia M. Mueller · Altdorf, DE

Key dates

Filing date	Oct 2, 2015
Grant date	May 23, 2017
Priority date	—
Expiry date	Nov 19, 2035

Classification

Technology area (CPC G)Physics
CPC primaryG06F7/49947
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

Arithmetic logic circuitry is provided for performing a floating point arithmetic add/subtract operation on first and second floating point numbers. The method includes: generating a guard digit for the first or second number by transforming the first and second numbers by a compressing function; determining a result depending on the arithmetic operation, a sum of the transformed floating point numbers, and first and second differences of the transformed floating point numbers, and determining a corresponding result plus one by additionally adding a value of one to the result; generating injection values for rounding the final result; generating injection carry values based on the transformed first and second numbers and the injection values; and selecting the final result from the result, the result plus one, and a least significant digit, based on the injection carry values and the end around carry signals.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.