Semiconductor structure with aligning mark and method of forming the same
US9659873B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 26, 2015 |
| Grant date | May 23, 2017 |
| Priority date | — |
| Expiry date | Aug 26, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2223/5446
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The present invention provides a semiconductor structure comprising a wafer and an aligning mark. The wafer has a dicing region which comprises a central region, a middle region surrounds the central region, and a peripheral region surrounds the middle region. The aligning mark is disposed in the dicing region, wherein the alignment mark is a mirror symmetrical pattern. The aligning mark comprises a plurality of second patterns in the middle region and a plurality of third patterns disposed in peripheral region, wherein each third pattern comprises a plurality of lines, and a width of the line is 10 times less than a width of the L-shapes. The present invention further provides a method of forming the same.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.